The present disclosure herein relates to a clock delay circuit, a delay locked loop, and a semiconductor memory device having the same.
A delay locked loop (DLL) is used for generating an internal clock in an electronic device. A typical DLL generates an internal clock synchronized with an external clock by delaying it by a predetermined time through a delay line. This DLL may be used for generating a signal for outputting data from a semiconductor memory device and for storing data therein.
In order to improve a data transfer rate between electronic devices, it is necessary to increase a frequency of an internal clock in the electronic device and also, in order to reduce errors occurring due to high-speed data transfer rate, it needs to accurately position a data valid window.
For example, in a semiconductor memory device, a data transfer rate may be increased by using an internal clock with a multiplied frequency of an external clock. In addition, errors occurring due to high speed data transfer may be reduced by using clocks with an accurate phase delay and accurate duty ratio. However, in the case that an internal clock frequency is increased, harmonic locking may occur during a locking operation of the DLL. Additionally, as a manufacturing process technology becomes more related to miniaturization, process variations may further affect manufacturing processes. Therefore, due to phase delay mismatching of a delay line in the DLL, it becomes more difficult to generate clocks with an accurate phase delay and uniform duty ratio.